As artificial intelligence (AI) and high-performance computing (HPC) continue their aggressive ascent, the semiconductor industry finds itself locked in an intense battle against an unexpected adversary: power delivery. While much of the public discourse focuses on algorithm optimization, accelerator scale, and semiconductor node scaling, a quiet crisis is brewing at the board and package levels. Modern kilowatt-class GPUs and accelerators demand monumental amounts of current at remarkably low voltages, pushing traditional power distribution networks (PDNs) to their absolute physical limits.
To address this compounding bottleneck, power electronics innovators are looking beyond standard surface-mount devices (SMDs). Among them is Saras Micro Devices, which is positioning its embedded passive technology—known as STILE—as a foundational element in solving the modern AI power puzzle. To understand the gravity of these engineering challenges and how embedded passives fit into the future of data center architecture, Electronic Design Senior Editor James Morra recently sat down with Shaun Bowers, Senior Vice President of Product Management at Saras Micro Devices and a veteran semiconductor executive with over 25 years of experience in advanced packaging.
Main Facts: The Anatomy of the AI Power Bottleneck
The fundamental physics governing electrical power delivery reveal a harsh reality for modern AI hardware: as power demands skyrocket, resistive losses scale exponentially.
Modern data center infrastructure relies heavily on a 48-V (or 54-V) backplane architecture. On individual accelerator boards, this high voltage is stepped down through a series of voltage regulator modules (VRMs). Typically, a 48V-to-12V VRM feeds a multitude of 12V-to-point-of-load (POL) VRMs arranged laterally around the main processor.
However, as silicon integration increases, thermal design power (TDP) climbs into multi-kilowatt territory. Simultaneously, advanced process nodes dictate lower operating voltages—frequently sitting between 0.6 V and 0.8 V. According to the foundational relationship $I = fracPV$, dropping the voltage while drastically raising the power causes the required current ($I$) to surge.
As massive currents flow through extended lateral pathways, $I^2R$ (resistive) losses generate unsustainable amounts of heat. Furthermore, traditional systems rely on sprawling hierarchies of passive components—such as bulk capacitors near VRMs and decoupling capacitors beneath the processor—to manage voltage stability and handle transient load spikes. These components devour critical board real estate, force power supplies further away from the compute load, and ultimately throttle overall system efficiency.
Chronology and Industry Evolution: From Lateral to Vertical and Embedded Architectures
The evolution of power delivery in high-performance computing has been driven by an ongoing quest to reduce parasitic resistance and inductance by physically moving power supplies closer to the processor core.
The Traditional Lateral Era: For decades, standard server architectures placed VRMs and their associated passive components laterally around the processor on the top side of the printed circuit board (PCB). While adequate for lower-power CPUs, this layout introduces excessive trace length, high parasitic impedance, and severe power losses under heavy, dynamic AI workloads.
The Rise of Vertical Power Delivery (VPD): Recognizing the limitations of lateral layouts, the industry began shifting toward Vertical Power Delivery (VPD). By relocating VRMs to the underside of the PCB—directly beneath ("in the shadow of") the processor—engineers significantly shortened the power delivery path. However, this migration created a spatial conflict: the underside of the board was already congested with the surface-mounted capacitors essential for transient response and noise decoupling.
The Package-Level and Embedded Era: To clear the way for VPD and further shrink the electrical loop, the industry is now moving passive components off the main PCB entirely and embedding them directly into the IC package substrate or internal layers of the board. Technologies like Saras Micro Devices’ STILE represent this next generational leap, integrating passives directly into the substrate matrix to sit immediately adjacent to the silicon die.
Supporting Data: The Physics of Resistance, Capacitance, and Temperature
Evaluating the viability of advanced power delivery architectures requires a deep dive into electrical, thermal, and mechanical constraints.
Overcoming Parasitic Impedance
When power supplies are separated from the processor by long traces and multiple board layers, parasitic inductance and resistance degrade transient response. When an AI accelerator transitions from an idle state to executing a heavy tensor operation, it draws an instantaneous surge of current. Without immediate charge replenishment, the voltage sags below the processor’s strict ripple envelope, risking system crashes.
Capacitor networks mitigate this by supplying immediate charge across various frequency ranges, each chosen for its specific impedance profile. However, surface-mounted passives take up valuable board space and introduce parasitic loop inductance. Substrate-embedded passives bypass these limitations by minimizing the physical distance between the energy storage and the load, effectively neutralizing parasitic resistance.
Thermal and Mechanical Trade-offs
Moving power conversion and passive integration closer to high-current SoCs exposes every component in the power path to extreme thermal stress. According to Shaun Bowers, evaluating these solutions requires balancing electrical parameters with complex multi-physics challenges:
Temperature Stability: Embedded components must operate reliably at elevated temperatures (often rated up to 125°C) without significant capacitance derating under bias.
Coefficient of Thermal Expansion (CTE): Device packages comprise multiple materials with varying thermal expansion rates. In high-heat AI server environments, mismatched CTE values can lead to severe mechanical warpage. Therefore, substrate-embedded passives must be engineered to withstand rigorous thermal cycling and reflow profiles without compromising structural integrity.
Official Responses: Insights from Industry Expert Shaun Bowers
In his discussion with Electronic Design, Shaun Bowers broke down the realities of modern power bottlenecks, the mechanics of package-level integration, and the future trajectory of data center power architectures.
When asked about the true definition of a power "bottleneck," Bowers pointed to a dual-layered crisis. At the macro level, he highlighted the growing mismatch between soaring data center power demands and the sluggish expansion of global electrical grid infrastructure. At the micro level, he emphasized the severe resistive losses within the PDN as TDP scales into multi-kilowatt ranges.
"To sustain growth and establish an economically viable business, it’s now critical to maximize the amount of compute per watt and minimize the cost per operation and token," Bowers explained. "Accomplishing this requires rethinking the PDN architecture at every step to maximize efficiency and minimize the associated heat load and power required for cooling."
Detailing the mechanics of Saras’ STILE technology, Bowers noted that these integrated passive modules are manufactured to match the precise thickness of the substrate in which they are embedded. Featuring 3D pass-through copper terminations and near-zero thermal capacitance derating, the current generation of STILE products primarily addresses the output capacitance needs of VRMs. Meanwhile, future iterations are already under development to handle high-frequency applications encompassing both decoupling capacitance and integrated inductance.
Discussing the engineering hurdles of package-level integration, Bowers stressed that system architects must adopt a multidisciplinary approach. Electrical performance cannot be viewed in a vacuum; it must be co-optimized with thermal management and mechanical reliability to prevent warpage and ensure long-term field reliability.
Implications: The Future of AI and High-Performance Computing Power
The ongoing transformation of power delivery networks carries profound implications for the future of AI hardware, data center economics, and semiconductor packaging.
Redefining Data Center Efficiency: As data center power consumption approaches the gigawatt threshold, efficiency is no longer just a technical metric—it is the primary economic limiter for AI deployment. Reducing resistive losses directly translates to lower operational expenditures, reduced cooling overhead, and a lower total cost of ownership per AI inference token.
The Evolution of Integrated Voltage Regulators (IVRs): Looking toward the horizon, Bowers predicts that the PDN will continue to disaggregate. While VPD serves as a vital bridge, the ultimate destination for high-performance processors will likely involve on-package or even on-die Integrated Voltage Regulators (IVRs). However, because IVRs are still in their infancy, substrate-embedded passives will play an indispensable role as a transitional and complementary technology, acting as a high-performance front-end for future integrated power stacks.
A Paradigm Shift in Packaging Supply Chains: The necessity for embedded passives forces closer collaboration between silicon foundries, substrate manufacturers, and power electronics specialists. Heterogeneous integration is expanding beyond logic and memory to include passive components, permanently altering how microelectronic packages are conceptualized, designed, and manufactured.
Ultimately, solving the AI power puzzle requires more than incremental efficiency gains; it demands a fundamental redesign of how electricity travels from the power grid to the heart of the silicon die. Through innovations like substrate-embedded passives, the semiconductor industry is laying the groundwork necessary to sustain the next generation of artificial intelligence and high-performance computing.
